linear integrated systems ? 4042 clipper court ? fremont, ca 94538 ? tel: 510 490 - 9160 ? fax: 510 353 - 0261 doc 201135 11/30/2015 rev#a9 ecn# 2n & sst 4117 4118 4119 features low power i dss <600 a (2n 4117 a ) minimum circuit loading i g ss <1 pa (2n 4117 a series) absolute maximum ratings ( note 3 ) @ 25c (unless otherwise noted) ga te - source or gate - drain voltage - 40v gate - current 50ma total device dissipation (de rate 2mw/oc above 25 oc ) 300mw storage temperature range - 55oc to+150oc lead temperature (1/16 from case for 10 seconds) 300oc electrical characteristics @ 25oc (unless otherwise noted) symbol characteristic 4 117 4118 4119 units conditions min max min max min max bv gss gate - source breakdown voltage - 40 -- - 40 -- - 40 -- v i g = - 1a v ds =0 v gs (off) gate - source cutoff voltage - 0.6 - 1.8 - 1 - 3 - 2 - 6 v ds =10v i d =1na i d s s saturation drain current ( note 2 ) 0.03 0.60 0.08 0.60 0.20 0.80 ma v ds =10v v gs =0 i gss gate reverse current 2N4117A, 2n4118a, 2n4119a -- - 1 -- - 1 -- - 1 pa v gs = - 20v v ds =0 -- - 2.5 -- - 2.5 -- - 2.5 na 150oc pn4117, pn4118, pn4119 sst4117, sst4118, sst4119 -- - 10 -- - 10 -- - 10 pa v gs = - 10v v ds =0 -- - 25 -- - 25 -- - 25 na 150oc g fs common - source forward transconductance 70 450 80 650 100 700 s v ds =10v v gs =0 f=1khz g os common - source output conductance -- 3 -- 5 -- 10 c iss common - source input capacitance ( note 4 ) -- 3 -- 3 -- 3 pf f=1mhz c rss common - source reverse transfer capacitance ( note 4) -- 1.5 -- 1.5 -- 1.5 2n /pn/sst 4117, 4118, 4119 ultra - high input impedance n - channel jfet amplifier 2n series sst series pn series to - 72 top view to - 92 top view sot - 23 top view 1 2 3 sot-23 top view d g s 1 2 3 d s g
linear integrated systems ? 4042 clipper court ? fremont, ca 94538 ? tel: 510 490 - 9160 ? fax: 510 353 - 0261 doc 201135 11/30/2015 rev#a9 ecn# 2n & sst 4117 4118 4119 *dimensions in inches 2N4117A, 2n4118a, 2n4119a to - 72 four lead pn4117, pn4118, pn4119 to - 92 sst4117, sst4118, sst4119 sot - 2 3 notes: 1. due to symmetrical geometry, these units may be operated with source and drain leads interchanged. 2. this parameter is measured during a 2 ms interval 100 ms after power is applied. (not a jedec condition.) 3. absolute maximum ratings are limiting values above which serviceability may be impaired. 4. not production tested, guaranteed by design. information furnished by linear integrated systems is believed to be accurate and reliable. however, no responsibility is as sumed for its use; nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent rights of linear integrated systems. 5. standard package dimensions : linear integrated systems (lis) is a 25 - year - old, third - generation precision semiconductor company providing high - quality discrete components. expertise brought to lis is based on processes and products developed at amelco, union car bide, intersil and micro power systems by company president john h. hall. hall, a protg of silicon valley legend dr. jean hoerni, was the director of ic development at union carbide, co - founder and vice president of r&d at intersil, and founder/president of micro power systems. 1 2 3 sot-23 dimensions in millimeters 0.89 1.03 1.78 2.05 1.20 1.40 2.10 2.64 0.37 0.51 2.80 3.04 0.89 1.12 0.013 0.100 0.085 0.180 0.55
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